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myson technology MTL004 (rev. 0.95) revision 0.95 - 1 - 2000/06/14 xga flat panel controller features general auto configuration of sampling clock frequency, phase, h/v center, as well as white balance. auto detection of present or non-present or over range sync signals and their polarities. composite sync separation and odd/even field detection of interlaced video. no external memory required. on-chip out put pll provide clock frequency fine-tune (inverse, duty cycle and delay). selection of serial 2-wire i 2 c or 3-wire serial or 8-bit direct host interface to 8-bit mcu. 3.3v supplier, 5v i/o tolerance in 208-pin pqfp package. input processor single rgb (24-bit) or dual rgb (48-bit) input rates up to 100mhz. support both non-interlaced and interlaced rgb graphic input signals .. compliant with digital lvds/ panellink tmds input interface. pc input resolution up to xga 1024x768 @85hz. video processor independent programmable horizonta l and vertical scaling up ratios from 1 to 32 built-in programmable gain control for white balance alignments. built-in programmable 8-bit gamma correction table. built-in programmable temporal color dithering. built-in programmable interpolation look-up table. support smooth panning under viewing window change. output processor single pixel (18/24-bit) or dual pixel (36/48-bit) per clock digital rgb output. built-in output timing generator with programmable clock and h/v sync. support vga/svga/x ga display resolution. overlay input interface with external osd controller. double scan capability for interlaced input. general description the MTL004 flat panel display (fpd) controller is an input format converter for tft-lcd monitor or lcd tv application which accepts 15-pin d-sub rgb graphic signals (through adc), or digital rgb graphic signals from panellink tmds receiver. it includes a rgb input processor, video scaling up processor , osd input interface and output display processor in 208-pin pqfp.
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 2 - 2000/06/14 block diagram applications this datasheet contains new product information. myson technology reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. rgb input zoom buffer ditherin g host interface mode detect auto calibration osd & output mux pc rgb to i2c bus to external osd rgb output MTL004 fpd monitor controller mtv212 8-bit mcu mtv130 osd lvds/panellink tmds receiver tft-lcd flat panel adc1 adc2 d-sub rgb graphic signals scale up gain contr ol gamma correct display timing generator
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 3 - 2000/06/14 1. pin connection nc *157 nc *158 gpio1 *159 gpio0 *160 pvss *161 ohsync *162 oclk *163 ovsync *164 g2in7 *165 g2in6 *166 g2in5 *167 g2in4 *168 g2in3 *169 g2in2 *170 g2in1 *171 dvdd *172 extdclk2 *173 dvss *174 extdclk1 *175 pvdd *176 g2in0 *177 g2out0 *178 pvss *179 g2out1 *180 g2out2 *181 g2out3 *182 dvdd *183 g2out4 *184 g2out5 *185 g2out6 *186 g2out7 *187 dvss *188 r2out0 *189 r2out1 *190 r2out2 *191 r2out3 *192 nc *193 rstz *194 pvdd *195 g1out0 *196 nc *197 g1out1 *198 pvss *199 g1out2 *200 g1out3 *201 g1out4 *202 g1out5 *203 pvdd *204 bussel0 *205 bussel1 *206 nc *207 pvss *208 MTL004 (208-pin pqfp) 052* pvss 051* ad6 050* ad7 049* ale 048* dvdd 047* b1out3 046* b1out2 045* dvss 044* b1out1 043* b1out0 042* pvdd 041* r1out7 040* r1out6 039* pvss 038* r1out5 037* r1out4 036* dvss 035* dvdd 034* hrdz 033* nc 032* dvss 031* hwrz 030* doez 029* dhsync 028* dvsync 027* dvdd 026* dhclk 025* dden 024* ddclk 023* dvss 022* nc 021* gpio2 020* gpio3 019* nc 018* osden 017* osdblu 016* dvdd 015* osdgrn 014* osdred 013* dvss 012* r1out3 011* r1out2 010* dvdd 009* r1out1 008* r1out0 007* g1out7 006* g1out6 005* pvss 004* osdint 003* nc 002* nc 001* nc 104* nc 103* nc 102* dvss 101* nc 100* dvdd 099* b1in2 098* b1in3 097* b1in4 096* b1in5 095* b1in6 094* b1in7 093* b2in0 092* b2in1 091* pvdd 090* b2in2 089* b2in3 088* b2in4 087* b2in5 086* b2in6 085* b2in7 084* pvss 083* b2out7 082* b2out6 081* b2out5 080* b2out4 079* dvdd 078* b2out3 077* b2out2 076* b2out1 075* dvss 074* b2out0 073* r2out7 072* dvdd 071* r2out6 070* r2out5 069* r2out4 068* dvss 067* irq 066* ad2 065* ad1 064* ad0 063* hcsz 062* pvdd 061* b1out7 060* b1out6 059* b1out5 058* b1out4 057* pvss 056* ad3 055* ad4 054* ad5 053* nc nc *105 nc *106 nc *107 tdie *108 pvss *109 b1in1 *110 b1in0 *111 r2in7 *112 r2in6 *113 r2in5 *114 r2in4 *115 r2in3 *116 r2in2 *117 r2in1 *118 r2in0 *119 r1in7 *120 r1in6 *121 r1in5 *122 r1in4 *123 r1in3 *124 clamp *125 r1in2 *126 dvss *127 r1in1 *128 tmdssel *129 nc *130 dvdd *131 r1in0 *132 g1in7 *133 g1in6 *134 g1in5 *135 g1in4 *136 g1in3 *137 g1in2 *138 g1in1 *139 g1in0 *140 vsync1 *141 ipclk1 *142 rawhs *143 nc *144 hsync1 *145 nc *146 nc *147 ipclk2 *148 hsync2 *149 vsync2 *150 pvdd *151 avdd *152 xo *153 xi *154 avss *155 nc *156
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 4 - 2000/06/14 2. pin description adc1 input interface (rgb or tmds input data) name type pin# description ipclk1 i 142 input pixel clock 1 vsync1 i 141 input vertical sync 1 hsync1/cs1 i 145 input horizontal or composite sync 1 r1in[7:0] i 120-124, 126,128, 132 red channel or tmds input data (single/dual adc) g1in[7:0] i 133-140 green channel or tmds input data (single/dual adc) b1in[7:0] i 94-99, 110-111 blue channel or tmds input data (single/dual adc) rawhs/sog i 143 input source hsync or input sync on green tdie i 108 tmds digital input enable nc o 130 no connection tmdssel o 129 tmds input select, active high clamp o 125 clamp pulse output for adc adc2 input interface (rgb or tmds input data) name type pin# description ipclk2 i 148 input pixel clock 2 vsync2 i 150 input vertical sync 2 hsync2/cs2 i 149 input horizontal or composite sync 2 r2in[7:0] i 112-119 red or tmds input data (single/dual adc) g2in[7:0] i 165-171, 177 green channel or tmds input data (single/dual adc) b2in[7:0] i 85-90, 92-93 blue or tmds input data (single/dual adc) nc i 144 no connection nc i 147 no connection nc i 146 no connection display output interface name type pin# description dden o 25 display data output enable dvsync o 28 display vertical sync output dhsync o 29 display horizontal sync output ddclk o 24 display output clock dhclk o 26 display half rate output clock doe# i 30 display port output enable, ? 1 ? will tri_state all display port output signals r1out[7:0] o 41-40 38-37, 12-11,9-8 red output even data , bit[7:2] for 6-bit panel g1out[7:0] o 7-6, 203-200, 198,196 green output even data , bit[7:2] for 6-bit panel b1out[7:0] o 61-58,47, 46,44,43 blue output even data , bit[7:2] for 6-bit panel r2out[7:0] o 73,71-69, 192-189 red output odd data , bit[7:2] for 6-bit panel g2out[7:0] o 187-184, 182-180, 178 green output odd data , bit[7:2] for 6-bit panel
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 5 - 2000/06/14 b2out[7:0] o 83-80, 78-76,74 blue output odd data , bit[7:2] for 6-bit panel host interface name type pin# description rst# i 194 system reset input, active low. ad[7:0] i/o 50-51, 54-56, 66-64 the address and data bus of 8-bit direct interface or 2-wire i 2 c / 3-wire series bus bit 2: sdao, 3-wire serial bus data out bit 1: sda, serial bus data / 3-wire serial bus data in bit 0: sck, serial bus clock hwr# i 31 host write strobe, active low hrd# i 34 host read strobe, active low ale i 49 host address latch enable for 8-bit direct bus hcs# i 63 host chip select bussel[1:0] i 206,205 bus mode selection. 0x: 3-wire bus, 10: i 2 c bus, 11: 8-bit direct bus irq o 67 interrupt request output osd interface name type pin# description oclk o 163 clock for external osd ovsync o 164 vertical sync for external osd ohsync o 162 horizontal sync for external osd osdred i 14 osd red input osdgrn i 15 osd green input osdblu i 17 osd blue input osdint i 4 osd intensity input osden i 18 osd overlay enable other interface name type pin# description xi i 154 oscillator frequency input xo o 153 oscillator frequency output extdclk1 i 175 external display clock input 1 extdclk2 i 173 external display clock input 2 gpio[3:0] i/o 20-21, 159-160 general purpose i/o or bit 1: advs, vertical sync for a/d converter bit 0: adhs, horizontal sync for a/d converter default: input direction nc - 1-3, 19, 22, 33, 53, 101, 103-107, 156-158, 193, 197, 207 no connection 3.3v power and ground name pin# description dvdd 10, 16, 27, 35, 48, 72, 79, 100, 131, 172, 183 digital power 3.3v dvss 13, 23, 32, 36, 45, 68, 75, 102, 127, 174, 188 digital ground pvdd 42, 62, 91, 151, 176, 195, 204 pad power 3.3v pvss 5, 39, 52, 57, 84, 109, 161, 179, 199, 208 pad ground
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 6 - 2000/06/14 avdd 152 analog power 3.3v avss 155 analog ground
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 7 - 2000/06/14 3. functional description 3.1 input processor general description the function of input interface is to provide the interface between MTL004 and external input devices. it can process non-interlaced and interlaced rgb graphic input, and digital rgb input compliant with digital lvds/ panellink tmds interface. 3.1.1 rgb input format the rgb input port works in two modes: single pixel mode (24 bits) and double pixel mode (48 bits). for single pixel mode, either ports r/g/ b1in[7:0] or r/g/b2in[7:0] selected by reg.16h/d0 can be chosen to be internally sampled. for the double pixel mode, besides ports r/g/ b1in[7:0], ports r/g/b2in[7:0] are also needed. the r/g/b1in ports are sampled at the rising edge of the rgb input clock, and the r/g/b2in ports are sampled at the falling edge. 3.1.2 tmds input format the digital rgb input port works just in the same way as sec 3.1.1 except that pin ? digital input enable dien ? is needed. with a flexible single or double pixel input interface, the supported format is up to true color, including 18 bit/pixel or 24 bit/pixel in 1 or 2 pixels/clock mode. 3.1.4 input hsync path in addition to the pins hsync1/2, MTL004 provides another pin rawhs to support the sync processor. in general, the synchronous hsync input for hsync1 or hsync2 generated by an adc may have a very narrow pulse width and a different polarity comparing to the original hsync provided by the source. the rawhs input provides the path of original hsync connection to MTL004, thus making sync processor in MTL004 working properly. 3.1.6 de-interlace mode for the interlace input, MTL004 features several de-interlacing algorithms for processing interlaced video data depending on the type of input images. toggle mode in this mode, only one field is displayed at the time. first field and second field are toggling displayed. the missing lines are calculated by duplicating the neighboring lines. this mode gives good quality for moving pictures. spatial mode in this mode, two fields are toggling displayed just like the toggle mode. the missing lines are calculated by interpolating the neighboring lines. this mode has a generally good quality for still and moving pictures. 3.1.7 sync processor the v/h sync processing block performs the functions of composite signal separation/insertion, sync inputs presence check, frequency counting, polarity detection and control. it contains a de-glitch circuit to filter out any pulse shorter than one osc period which is treated as noise among v/h sync pulses. v/h sync frequency counter MTL004 can measure vsync/hsync frequency counted in proper clock and save the information in the register. users can read the figure and calculate vsync/hsync frequency as following formulas: f vsync = f osc / n vsync 5 1/256 f hsync = f osc / n hsync 5 8 ,where f vsync : vsync frequency f hsync : hsync frequency f osc : oscillator clock with 14.31818 mhz
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 8 - 2000/06/14 n vsync : counted number of vsync n hsync : counted number of hsync v/h sync presence check this function checks the input vsync, where vpre flag is set when vsync is over 40hz or cleared when vsync is under 10hz and the input hsync, where hpre flag is set when hsync is over 10khz or cleared when hsync is under 10hz. v/h polarity detect this function detects the input vsync/hsync high and low pulse duty cycle. if the high pulse duration is longer than that of low pulse, the negative polarity is asserted; otherwise, positive polarity is asserted. composite sync separation/insertion MTL004 continuously monitors the input hsync. if the input vsync can be extracted from it, a cvpre flag is set. MTL004 can insert hsync pulse during composite vsync ? s active time and the insertion frequency can adapt to the original hsync ? s. 3.1.8 auto tune auto tune function consists of auto position which automatically centering the screen and auto calibration which contains phase calibration, histogram, min/max value, and pixel grab that are described in the following paragraphs. with such auto adjustment support it is possible to measure the correct phase, frequency, gain, and offset of adc. the horizontal and vertical back porches of input image and the horizontal and vertical active regions can also be measured. firmware can adjust input image registers automatically by reading auto tune ? s registers in single or burst mode. auto position MTL004 provides horizontal/vertical back porch and active region values. users can use these values to set input sample registers to aid in centering the screen automatically. phase calibration MTL004 provides auto calibration registers to measure the quality of current adc ? s phase and frequency. the biggest auto calibration registers value means the right value of adc ? s phase and frequency. MTL004 has two kinds of algorithms to calculate auto calibration ? s value. one is traditional difference method , another is myson ? s proprietary method. the latter one is recommended for a better performance. histogram histogram is the total number of input pixels below/above one threshold value for individual r, g, b colors. this advanced function helps firmware to analyze adc performance. usually firmware can use the information to measure adc ? s noise margin, adjust its offset and gain, or even aid in the mode detection. min/max value min/max value is the minimum or maximum pixel value within the specified input active image region for each rgb channel. this information is usually used to adjust adc ? s offset and gain. pixel grab pixel grab means user can grab a single input pixel at any one point. the position of the point can be programmed by the user. this is another traditional method to measure adc ? s phase and frequency.
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 9 - 2000/06/14 3.2 video processor general description MTL004 possesses a powerful and programmable video processor by providing the following functions: scaling up, gain control, brightness control, gamma correction, and dithering control. the block diagram of video processor is as follows: fig. 3.2.1 video processor block diagram 3.2.1 scaling MTL004 provides scaling function ranging from 1 to 32 for up scaling, and for both horizontal and vertical processing. for scaling up, both horizontal and vertical processing, MTL004 provides four methods: pass mode : image will be passed through without taking scaling factor into account. duplicate mode : image will be scaled up based on the scaling factor. every point of output image comes from the input. in this method, the output image will have a good contrast but the picture could be non-uniformed. bilinear mode : image will be scaled up based on the scaling factor. every point of output image data will be filtered by bilinear filter. in this method, the output image will have a good scaling quality but the picture could be blurred. interpolation table mode : image will be scaled up based on the scaling factor. the user-defined filter will filter every point of output image data. in this mode, every output point is calculated based on the 3 input points. input pixels: i k-1 i k i k+1 output pixels: y l-1 y l y l+1 gain brightness gamma dithering scaling interpolation table scaling factor brightness factor gamma table gain factor dithering table a l b l c l
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 10 - 2000/06/14 ,where y l =a l *i k-1 +b l *i k +c l *i k+1 and a, b, c are the scaling factors from interpolation table fig. 3.2.2 scaling filter 3.2.2 gain/brightness control MTL004 provides gain and brightness control to adjust the contrast and brightness of output color by programming the gain and brightness coefficients. this adjustment is applied to rgb colors individually. auto-white balance can be achieved by using this function. 3.2.3 gamma correction gamma correction is used to compensate the non-linearity of lcd display panel. MTL004 contains an 8-bit gamma table to fix this phenomenon. 3.2.4 color dithering MTL004 supports true color (8 bits per color) or high color (6 bits per color) display. in the latter case, users can turn on dithering function to avoid artificial contour due to truncation. the dithering function works in two modes: static dithering: dithering coefficient is fixed. temporal dithering: dithering coefficient is time dependent. 3.3 output processor general description output processor provides the interface for both lcd panel and osd controller. the output frame rate must be equal to the input frame rate and output display time must be equal to input display time since there is no frame buffer present.
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 11 - 2000/06/14 3.3.1 display timing generation because of no frame buffer, output displaying timing is locked by input timing and output frame rate is equal to input frame rate. users must program output timing and lock position to make sure that line buffer will not overflow or underflow. MTL004 can automatically calculate display horizontal total count to make the output timing calculation easier. MTL004 also provides line buffer overflow/underflow status for calibrating lock position. fig. 3.2.2 display timing modes 3.3.2 osd overlay MTL004 allows the integration of overlay data with the scaled output pixel stream. it provides a fully compatible osd interface. individual osd clock, osd hsync and osd vsync are sent to external osd device. MTL004 receives osd enable, osd red, osd green, osd blue, and osd intensity from external osd device. 3.3.3 rgb out put format MTL004 output interface consists of two pixel ports, each containing red, green, and blue color information with a resolution of 6/8 bits per color. these two ports are port1 and port2 respectively. the control signals for the output port are display horizontal sync signal (dhsync) , display vertical sync signal (dvsync) and display data enable signal (dden). all the signals mentioned above are synchronous to the output clock. the output timing relative to the active edge of the output clock is programmable. there are two rgb output formats: single pixel mode is designed to support tft panels with single pixel input. only port1 is active. the frequency of dclk is equal to internal display clock. dual pixel mode is designed to support tft panels with dual pixel input. port1 and port2 are used. the first pixel is at port1, with the second at port2. x x: lock position input frame output frame
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 12 - 2000/06/14 ddclk dden r1out/g1out /b1out 000 rgb0 rgb1 rgb2 rgb3 rgb4 dden dhclk ddclk r1out/g1out /b1out 000 rgb0 rgb2 rgb4 rgb6 rgb8 r2out/g2out /b2out 000 rgb1 rgb3 rgb5 rgb7 rgb9 single port dual port fig. 3.2.3 display data timing 3.5 host interface
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 13 - 2000/06/14 general description the main function of host interface is to provide the interface between MTL004 and external cpu by 2-wire i 2 c bus or 3-wire series bus or 8-bit direct bus selected by the input pins bussel[1:0]. it can generate all the i/o decoded control timing to control all the registers in MTL004. the other function is screen write, which allows users to clear frame buffer, and display output as well. 3.5.1 i 2 c serial bus the i 2 c serial interface use 2 wires, sck (clock) and sda(data i/o). the sck is used as the sampling clock and sda is a bi-directional signal for data. the communication must be started with a valid start condition, concluded with stop condition and acknowledged with ack condition by receiver. the i 2 c bus device address of MTL004 is 0111010x. ad[0] sck , serial bus clock. ad[1] sda, bi-directional serial bus data. the start condition means a high to low transition of sda when sck is high , the stop condition means a low to high transition of sda when sck is high. and data of sda only changes when sck is low. ref. fig.3.5.1. fig. 3.5.1 start, stop ,and data definition the i 2 c interface supports random write, sequential write, current address read, random read and sequential read operations. random write for random write operation, it contains the slave address with r/w bit set to 0 and the word address which is comprised of eight bits that provides the access to any one of the 256 bytes in the selected memory range. upon receipt of the word address, MTL004 responds with an acknowledge and waits for the next eight bits of data again, responding with an acknowledge, and then the master generates a stop condition. ref. fig.3.5.2. sda sck start data change data change stop
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 14 - 2000/06/14 fig. 3.5.2 random write sequential write the initial step of sequential write is the same as random write, after the receipt of each word data, MTL004 will respond with an acknowledge and then internal address counter will increment by one for next data write. if the master stops writing data, it will generate stop condition. ref. fig. 3.5.3. fig. 3.5.3 sequential write current address read MTL004 contains an address counter which maintains the last access address incremented by one. if the last access address is n, the read data should access from address n+1. upon receipt of the slave address with r/w bit set to 1, MTL004 generates an acknowledge and transmits the eight bits data. after receiving data the master will generate a stop condition instead of an acknowledge. ref. fig. 3.5.4. fig. 3.5.4 current address read s t a r t a c k slave address data r sda s t o p s t a r t a c k a c k a c k s t o p slave address word address data w sda sda s t a r t a c k a c k a c k slave address word address data n w data n+1 s t o p a c k a c k data n+x
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 15 - 2000/06/14 random read the operation of random read allows access to any address. before the reading data operation, it must issue a ? dummy write ? operation ? the master issues the start condition, slave address and then the word address it is to read. after the word address acknowledge, the master generating a start condition again and slave address with r/w bit is set to 1. MTL004 then transmits the 8 bits of data. upon the completion of receiving data, the master will generate a stop condition instead of an acknowledge. ref. fig 3.5.5. fig. 3.5.5 random read sequential read the initial step can be as either current address read or random read. the first read data is transmitted in the same manner as for other read methods. however, the master generates an acknowledge indicating it requires more data to read. MTL004 continues to output data for each acknowledge received. the output data is sequential and the internal address counter increments by one for next read data. ref. fig. 3.5.6. fig. 3.5.6 sequential read 3.5.2 3-wire serial bus the 3-wire serial interface use 3 wires, sck (clock) and sda(data i) and sdao(data o). the sck is used as the sampling clock, sda is an input signal for data, and sdao is an output signal for data. the handshaking protocol is the same as for the 2-wire i 2 c serial bus. ad[0] sck, serial bus clock. ad[1] sda, serial bus dat a in. ad[2] sdao, serial bus data out. 3.5.3 8-bit direct bus the direct bus use ad[7:0], hwr#, hrd#, ale, hcs# as the interface with host. ale is used to latch read or write address from ad[7:0] and hrd#, hwr# to access data. ref. fig. 3.5.7. ad[7:0] address and data multiplex bus. s t a r t a c k a c k a c k slave address word address w sda s t a r t slave address r data s t o p s t a r t a c k slave address data n r sda data n+1 a c k a c k data n+x s t o p
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 16 - 2000/06/14 hrd# cpu read data strobe, active low. hwr# cpu write data strobe, active low. ale ale =1 latch read or write address, ale=0 represents i/o data. hcs# enable signal for cpu access, active low. fig. 3.5.7 direct bus timing 3.5.4 interrupt MTL004 supports one interrupt output signal (irq) which can be programmed to provide sync related or function status related interrupts to the system. upon receiving the interrupt request, firmware needs to firstly check the interrupt event by reading the interrupt flag control registers (reg. e8h and e9h) to decide what events are happening. after the operation is finished, firmware needs to clear interrupt status by writing the same registers reg. e8h and e9h. furthermore, by using the interrupt flag enable registers (reg. eah and ebh), each interrupt event can be masked. 3.5.5 bi-directional gpio MTL004 supports four general purpose input and output (gpio) pins gpio[3:0] on chip. the gpio[3:0] pins are bi-directional gpio pins. there are two functions for gpio[1:0] pins. one is to set them as bi-directional gpio pins, and the other is to set them as composite decoded vsync/hsync for a/d converters in vga input path. the data and i/o direction of gpio[3:0] pins are respectively controlled by reg. f4h and f5h, and each bit in registers is respectively mapped to gpio[3:0] one by one. the following description is the process to control gpio[0] and gpio[2] in detail, and the control processes of gpio[1] and gpio[3] are also the same as follows respectively. bi-directional gpio control process q setting reg. f5h/d2 = 0 or 1 to assign gpio[2] as input or output. q writing data to reg. f4h/d2 when gpio[2] is assigned to output status, otherwise reading data from reg. f4h/d2 when gpio[2] is input. advs/adhs output control process q setting reg. f5h/d0= 1 to assign gpio[0] as output. q setting reg. f6h/d0 = 0 to select output source from reg. f4h/d6 or setting it as 1 to make gpio[0] pin to output adhs which is hsync signal decoded from vga input composite signal by the MTL004. q writing data to f4h/d0 when gpio[0] is assigned to output only gpio pin, that is, f6h/d0 = 0 and f5h/d0 = 0. if f6h/d0 is set to 1, the gpio[0] pin outputs adhs for ad converters in vga input path. 3.5.6 update register contents i/o write operation to some consecutive register set can have the ? double buffer ? effect by setting the reg. c1h/d4. written data is first stored in an intermediate bank of latches and then transferred to the active register set by setting reg. c1h/d1-0. ad[7:0] data address ale hwr/hrd
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 17 - 2000/06/14 3.6 on-chip pll general description the MTL004 needs two clock sources to drive synchronous circuits on chip. these clocks are generated from the internal phase lock loop (pll) circuits with reference to the oscillator clock which is applied to pin xi and xo by an external quartz crystal at 14.31818 mhz. first one is the same as to the oscillator clock at frequency (14.31818 mhz) to detect and measure graphic vertical and horizontal sync frequency, polarity as well as presence. the second is the display clock for display controller on chip and output signals to lcd panel. 3.6.1 reference clock it is the counting basis of counter values in sync processor such as vs and hs period count registers; that is, the read back values from these registers must multiply the period of this clock to estimate vs and hs frequency. incorporating with polarity and frequency information of vs and hs, it can show the input graphic image mode and pixel clock frequency. 3.6.2 displa y clock this clock is the synchronous clock for lcd panel. according to the lcd panel resolution of applications, the display clock range is from 50 mhz to 100 mhz by means of choosing a set of appropriate values for m, n as well as r. the formula used to calculate the desired frequency of display clock is as follows: f mclk = f osc 5 (m+2)/(n+2) 5 1/r where f mclk : the desired display clock f osc : oscillator clock with 14.31818 mhz m : post-divider ratio n : pre-divider ratio r : optional divider ratio
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 18 - 2000/06/14 4. register description input control registers address mode registers reset value 00h r/w input image vertical active line start - low 20h 01h r/w input image vertical active line start - high 00h 02h r/w input image vertical active lines - low e0h 03h r/w input image vertical active lines - high 01h 04h r/w input image horizontal active pixel start - low 8bh 05h r/w input image horizontal active pixel start - high 00h 06h r/w input image horizontal active pixels - low 80h 07h r/w input image horizontal active pixels - high 02h 10h r/w input image control register 0 00h 11h r/w input image control register 1 00h 12h r/w input image control register 2 00h 13h r/w input image control register 3 00h 14h r/w input image control register 4 00h 15h r/w input image control register 5 00h 16h r/w input image control register 6 00h 1ah r/w input delay control 2 00h 1ch r/w hs1 sample window forward extend 00h 1dh r/w hs1 sample window backward extend 00h 1fh ro input image status register - 20h r/w input image back porch guard band 00h 21h r/w input image front porch guard band 00h frame sync registers address mode registers reset value 2ch r/w input image vertical lock position - low 22h 2dh r/w input image vertical lock position - high 00h 2eh r/w input image horizontal lock position - low 00h 2fh r/w input image horizontal lock position - high 00h auto calibration registers address mode registers reset value 30h r/w auto calibration control 0 80h 31h r/w auto calibration control 1 00h 34h ro auto calibration red value - byte 0 - 35h ro auto calibration red value - byte 1 - 36h ro auto calibration red value - byte 2 - 37h ro auto calibration red value - byte 3 - 38h ro auto calibration green value - byte 0 - 39h ro auto calibration green value - byte 1 - 3ah ro auto calibration green value - byte 2 - 3bh ro auto calibration green value - byte 3 - 3ch ro auto calibration blue value - byte 0 - 3dh ro auto calibration blue value - byte 1 - 3eh ro auto calibration blue value - byte 2 - 3fh ro auto calibration blue value - byte 3 - 40h r/w pixel grab v reference position - low 00h 41h r/w pixel grab v reference position - high 00h
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 19 - 2000/06/14 42h r/w pixel grab h reference position - low 00h 43h r/w pixel grab h reference position - high 00h 44h r/w histogram reference color - red 00h 45h r/w histogram reference color - green 00h 46h r/w histogram reference color - blue 00h sync processor registers address mode registers reset value 48h r/w sync processor control 00h 49h r/w auto position control 00h 4ah r/w auto position reference color - red 00h 4bh r/w auto position reference color - green 00h 4ch r/w auto position reference color - blue 00h 4eh r/w clamp pulse control 0 00h 4fh r/w clamp pulse control 1 00h 50h ro input vs period count by refclk - low - 51h ro input vs period count by refclk - high - 52h ro input v back porch count by input hs - low - 53h ro input v back porch count by input hs - high - 54h ro input v active lines count by input hs - low - 55h ro input v active lines count by input hs - high - 56h ro input v total lines count by input hs - low - 57h ro input v total lines count by input hs - high - 58h ro input hs period count by refclk - low - 59h ro input hs period count by refclk - high - 5ah ro input h back porch count by input pixel clock - low - 5bh ro input h back porch count by input pixel clock - high - 5ch ro input h active pixels count by input pixel clock - low - 5dh ro input h active pixels count by input pixel clock - high - 5eh ro input h total pixels count by input pixel clock - low - 5fh ro input h total pixels count by input pixel clock - high - display control registers address mode registers reset value 60h r/w display vertical total - low 48h 61h r/w display vertical total - high 03h 62h r/w display vertical sync end- low 05h 63h r/w display vertical sync end - high 00h 64h r/w display vertical active start - low 22h 65h r/w display vertical active start - high 00h 66h r/w display vertical active end - low 22h 67h r/w display vertical active end - high 03h 70h r/w display horizontal total - low 2bh 71h r/w display horizontal total - high 05h 72h r/w display horizontal sync end - low 10h 73h r/w display horizontal sync end - high 00h 74h r/w display horizontal active start - low 27h 75h r/w display horizontal active start - high 01h 76h r/w display horizontal active end - low 27h 77h r/w display horizontal active end - high 05h
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 20 - 2000/06/14 7fh r/w nfb timing control 60h 88h r/w output image control register 0 01h 89h r/w output image control register 1 00h 8ah r/w output image control register 2 00h 90h r/w color gain control - red 80h 91h r/w color gain control - green 80h 92h r/w color gain control - blue 80h 93h r/w brightness control - red 00h 94h r/w brightness control - green 00h 95h r/w brightness control - blue 00h 9fh r/w gamma table data port - a0h r/w osd control register 0 08h a1h r/w osd control register 1 00h a4h r/w output invert control 00h a5h r/w output tri-state control 00h a6h r/w output clocks delay adjustment 00h a7h r/w output clocks duty cycle adjustment 00h a9h r/w output miscellaneous control 00h aah r/w output vertical line number - low ffh abh r/w output vertical line number - high 02h ach ro output horizontal total pixel number ? low - adh ro output horizontal total pixel number ? high - aeh ro output horizontal total residue number ? low - afh ro output horizontal total residue number - high - zoom control registers address mode registers reset value b0h r/w zoom control register 0 66h b1h r/w zoom control register 1 00h b4h r/w zoom vertical scale ratio - low e0h b5h r/w zoom vertical scale ratio - high 9fh b6h r/w zoom horizontal scale ratio - low e8h b7h r/w zoom horizontal scale ratio - high 9fh bfh r/w interpolation table data port - host control registers address mode registers reset value c1h r/w host control register 1 00h cbh ro host access mode status - clock control registers address mode registers reset value e0h r/w clock control register 00h e1h wo clock synthesizer value load - e2h r/w clock synthesizer n value 0bh e3h r/w clock synthesizer m value 32h e6h r/w clock synthesizer r value 00h
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 21 - 2000/06/14 interrupt control registers address mode registers reset value e8h r/w sync interrupt flag control 00h e9h r/w general interrupt flag control 00h eah r/w sync interrupt enable 00h ebh r/w general interrupt enable 00h ech r/w hs frequency change interrupt compare 00h miscellaneous registers address mode registers reset value f1h r/w power management control 00h f4h r/w gpio control register 00h f5h r/w gpio direction control 00h f6h r/w gpio misc control 00h input image vertical active line start - low (address 00h) (r/w) it defines the low byte of the start position of the vertical active window. d7-0 iv_act_ start[7:0] input image vertical active line start - high (address 01h) (r/w) it defines the high byte of the start position of the vertical active window. d7-3 reserved d2-0 iv_act_ start[10:8] input image vertical active lines - low (address 02h) (r/w) it defines the low byte of the number of active lines of the vertical active window. d7-0 iv_act_ len[7:0] input image vertical active lines - high (address 03h) (r/w) it defines the high byte of the number of active lines of the vertical active window. d7-3 reserved d2-0 iv_act_ len[10:8] input image horizontal active pixel start - low (address 04h) (r/w) it defines the low byte of the start position of the horizontal active window. d7-0 ih_act_ start[7:0] input image horizontal active pixel start - high (address 05h) (r/w) it defines the high byte of the start position of the horizontal active window. d7-3 reserved
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 22 - 2000/06/14 d2-0 ih_act_ start[10:8] input image horizontal active pixels - low (address 06h) (r/w) it defines the low byte of the number of active pixels of the horizontal active window. d7-0 ih_act_ width[7:0] input image horizontal active pixels - high (address 07h) (r/w) it defines the high byte of the number of active pixels of the horizontal active window. d7-3 reserved d2-0 ih_act_ width[10:8] input image control register 0 (address 10h) (r/w) d7 force to 0 d6 reserved d5 digital rgb 6 bit mode 0: 8 bits 1: 6 bits d4 digital rgb mode select 0: rgb input from adc 1: rgb input from panel link d3 force to 0 d2 reserved d1 force to 0 d0 adc configuration 0: double pixel mode 1: single pixel mode input image control register 1 (address 11h) (r/w) d7 reserved d6-5 reserved d4 de-interla ce mode select 0: spatial filtering write mode 1: toggle field write mode d3-1 reserved d0 reserved input image control register 2 (address 12h) (r/w)
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 23 - 2000/06/14 d7 input odd field invert 0: normal 1: invert d6 external input interlace select 0: non-interlace 1: interlace d5 external input vsync polarity 0: active low 1: active high d4 external input hsync polarity 0: active low 1: active high d3 input odd field source 0: from internal detection 1: from external pin. d2 input interlace source 0: from internal detection 1: from register setting (d6) d1 input vsync polarity source 0: from internal detection 1: from register setting (d5) d0 input hsync polarity source 0: from internal detection 1: from regist er setting (d4) input image control register 3 (address 13h) (r/w) d7 active position area for auto position in tmds 0: from internal detection 1: from external data enable (tdie) d6-4 reserved d3 data enable in tmds select 0: from pin tdie 1: from pin rawhs d2 sync on green select 0: select normal hsync/ composite sync 1: select sync on green d1 input vertical timing based on vsync 0: leading edge 1: trailing edge d0 input horizontal timing based on hsync 0: leading edg e 1: trailing edge input image control register 4 (address 14h) (r/w)
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 24 - 2000/06/14 d7 input odd field detection point 0: at the start of vsync pulse. 1: at the end of vsync pulse. d6 input image port a, b data and clocks swap 0: normal 1: swap d5 res erved d4 reserved d3 input image port a, b v/h sync swap 0: normal 1: swap d2-0 reserved input image control register 5 (address 15h) (r/w) d7 horizontal pixel valid select 0: from internal programming 1: from external href/tdie d6-0 reserved input image control register 6 (address 16h) (r/w) d7 bit order in port b 0: normal 1: reverse d6 bit order in port a 0: normal 1: reverse *d5 flush line buffer enable 0: disable 1: enable d4-3 reserved d2 adc hs polarity invert when d1=1 0: active low 1: active high d1 raw hs path enable 0: disable 1: enable d0 input image port selection in single pixel mode (for double pixel mode, this bit has no function.) 0: port a 1: port b input delay control 2 (address 1ah) (r/w)
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 25 - 2000/06/14 d7-4 input vsync delay adjustment 1111: 15ns gate delay 1110: 14ns gate delay 1101: 13ns gate delay 1100: 12ns gate delay 1011: 3 idclks delay 1010: 2 idclks delay 1001: 1 idclk delay 1000: 8ns gate delay 0111: 7ns gate delay 0110: 6ns gate delay 0101: 5ns gate delay 0100: 4ns gate delay 0011: 3ns gate delay 0010: 2ns gate delay 0001: 1ns gate delay 0000: no delay d3-0 input hsync delay adjustment 16 steps to change, each of them is 1ns delay/s tep. input hs pulse width forward extend (address 1ch) (r/w) d7-0 input hs pulse width forward extend by idclk hs1fwext[7:0]: used when interlace first/second field detection. input hs pulse width backward extend (address 1dh) (r/w) d7-0 input hs pulse width backward extend by idclk hs1bwext[7:0]: used when interlace first/second field detection. input image status register (address 1fh) (ro) d7 display vsync monitor show display vsync signal directly. d6 input vsync monitor show input vsync signal directly. d5 external input interlace status 0: non-interlace 1: interlace d4 extracted cvsync present status 0: not present 1: present d3 external input vsync present status 0: not present 1: present d2 external inpu t hsync present status 0: not present 1: present d1 external input vsync polarity status
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 26 - 2000/06/14 0: active low 1: active high d0 external input hsync polarity status 0: active low 1: active high input image back porch guard band (address 20h) (r/w) d7-0 input image back porch guard band by idclk hbpgb[7:0]: used in auto position detection to mask out unwanted data. input image front porch guard band (address 21h) (r/w) d7-0 input image front porch guard band by idclk hfpgb[7:0]: used in auto position detection to mask out unwanted data. input image vertical lock position - low (address 2ch) (r/w) it defines the low byte of the number of input lines where display image timing synchronizes the input image source. d7-0 ipv_lock_ pos[7:0] input image vertical lock position - high (address 2dh) (r/w) it defines the high byte of the number of input lines where display image timing synchronizes the input image source. d7-3 reserved d2-0 ipv_lock_ pos[10:8] input image horizontal lock position - low (address 2eh) (r/w) it defines the low byte of the number of input pixel clocks where display image timing synchronizes the input image source. d7-0 iph_lock_ pos[7:0] input image horizontal lock position - high (address 2fh) (r/w) it defines the high byte of the number of input pixel clocks where display image timing synchronizes the input image source. d7-3 reserved d2-0 iph_lock_ pos[10:8] auto calibration control 0 (address 30h) (r/w) d7 pixel grab ready flag (ro) 0: ready 1: not ready d6 pixel grab update enable 0: stop updating
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 27 - 2000/06/14 1: continue updating d5 threshold select used in histogram mode or min/max mode. 0: high bound / max 1: low bound / min d4 phase calibration method select 0: myson p roprietary method 1: difference value method d3-2 auto calibration modes select the measured value is available one item at a time, selected as shown: 00: phase calibration mode 01: histogram mode 10: min/max mode 11: pixel grab mode d1 auto calibration burst mode enable ( except pixel grab mode) 0: single mode 1: burst mode d0 auto calibration enable (w) ( except pixel grab value) 0: disable 1: enable auto calibration ready flag (r) 0: ready 1: not ready auto calibration control 1 (address 31h) (r/w) d7-3 reserved d2-0 mask lsbs of input image select it is used only for phase calibration to mask noise. 000: no mask 001: mask bit0 010: mask bit0 ,1 011: mask bit0 ,1,2 100: mask bit0 ,1,2,3 101: mask bit 0 ,1,2,3,4 110: mask bit0 ,1,2,3,4,5 111: mask bit0 ,0,1,2,3,4,5,6 auto calibration red value - byte 0 (address 34h) (ro) it states the byte 0 of the number of phase calibration red value in one frame or the byte 0 of the number of histogram red value in one frame or the pixel grab red value in one frame of non_interlace mode or first field of interlace mode. d7-0 calval_ r[7:0] auto calibration red value - byte 1 (address 35h) (ro)
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 28 - 2000/06/14 it states the byte 1 of the number of phase calibration red value in one frame or the byte 1 of the number of histogram red value in one frame or the pixel grab green value in one frame of non_interlace mode or first field of interlace mode. d7-0 calval_ r[15:8] auto calibration red value - byte 2 (address 36h) (ro) it states the byte 2 of the number of phase calibration red value in one frame or the byte 2 of the number of histogram red value in one frame or the pixel grab blue value in one frame of non_interlace mode or first field of interlace mode. d7-0 calval_ r[23:16] auto calibration red value - byte 3 (address 37h) (ro) it states the byte 3 of the number of phase calibration red value in one frame. d7-6 reserved d5-0 calval_ r[29:24] auto calibration green value - byte 0 (address 38h) (ro) it states the byte 0 of the number of phase calibration green value in one frame or the byte 0 of the number of histogram green value in one frame or the pixel grab red value in second field of interlace mode. d7-0 calval_ g[7:0] auto calibration green value - byte 1 (address 39h) (ro) it states the byte 1 of the number of phase calibration green value in one frame or the byte 1 of the number of histogram green value in one frame or the pixel grab green value in second field of interlace mode. d7-0 calval_ g[15:8] auto calibration green value - byte 2 (address 3ah) (ro) it states the byte 2 of the number of phase calibration green value in one frame or the byte 2 of the number of histogram green value in one frame or the pixel grab blue value in second field of interlace mode. d7-0 calval_ g[23:16] auto calibration green value - byte 3 (address 3bh) (ro) it states the byte 3 of the number of phase calibration green value in one frame. d7-6 reserved d5-0 calval_ g[29:24] auto calibration blue value - byte 0 (address 3ch) (ro) it states the byte 0 of the number of phase calibration blue value in one frame or
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 29 - 2000/06/14 the byte 0 of the number of histogram blue value in one frame or the min/max red value in one frame. d7-0 calval_ b[7:0] auto calibration blue value - byte 1 (address 3dh) (ro) it states the byte 1 of the number of phase calibration blue value in one frame or the byte 1 of the number of histogram blue value in one frame or the min/max green value in one frame. d7-0 calv al_ b[15:8] auto calibration blue value - byte 2 (address 3eh) (ro) it states the byte 2 of the number of phase calibration blue value in one frame or the byte 2 of the number of histogram blue value in one frame or the min/max blue value in one frame. d7-0 calval_ b[23:16] auto calibration blue value - byte 3 (address 3fh) (ro) it states the byte 3 of the number of phase calibration blue value in one frame. d7-6 reserved d5-0 calval_ b[29:24] pixel grab v reference position - low (address 40h) (r/w) it states the low byte of vertical reference position in pixel grab mode. d7-0 vgrab_ pos[7:0] pixel grab v reference position - high (address 41h) (r/w) it states the high byte of vertical reference position in pixel grab mode. d7-3 reser ved d2-0 vgrab_ pos[10:8] pixel grab h reference position - low (address 42h) (r/w) it states the low byte of horizontal reference position in pixel grab mode. d7-0 hgrab_ pos[7:0] pixel grab h reference position - high (address 43h) (r/w) it states the high byte of horizontal reference position in pixel grab mode. d7-3 reserved d2-0 hgrab_ pos[10:8]
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 30 - 2000/06/14 histogram reference color - red (address 44h) (r/w) it states the histogram reference red color in histogram mode. d7-0 hist_ r[7:0] histogram reference color - green (address 45h) (r/w) it states the histogram reference green color in histogram mode. d7-0 hist_ g[7:0] histogram reference color - blue (address 46h) (r/w) it states the histogram reference blue color in histogram mode. d7-0 hist_ b[7:0] sync processor control (address 48h) (r/w) d7-2 reserved d1-0 sync source 00: from h/v sync 01: from cvsync (composite sync) 1x: auto switch to cvsync when cvsync is present, but vsync not. auto position control (address 49h) (r/w) d7-2 reserved d1 auto position burst mode enable 0: single mode 1: burst mode d0 auto position enable (w) 0: disable 1: enable auto position ready flag (r) 0: ready 1: not ready auto position reference color - red (address 4ah) (r/w) it defines the red component color for selecting between black and non-black pixels. d7-0 ref_color_ red[7:0] auto position reference color - green (address 4bh) (r/w) it defines the green component color for selecting between black and non-black pixels. d7-0 ref_color_ green[7:0] auto position reference color - blue (address 4ch) (r/w)
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 31 - 2000/06/14 it defines the blue component color for selecting between black and non-black pixels. d7-0 ref_color_ blue[7:0] clamp pulse control 0 (address 4eh) (r/w) d7 clamp pulse mask 0: normal 1: mask out clamp pulse d6 clamp pulse start reference edge 0: from input hsync trailing edge. 1: from input hsync leading edge. d5 clamp pulse output polarity 0: active high 1: active low d4-0 clamp pulse start start of clamp pulse after the selected edge of input hsync by input dclk. clamp pulse control 1 (address 4fh) (r/w) d7-5 reserved d4-0 clamp pulse width to adjust clamp pulse width by input dclk. input vs period count by refclk - low (address 50h) (ro) it states the low byte of the number of refclk of the vertical sync period measurement. d7-0 vsprd[7:0] input vs period count by refclk - high (address 51h) (ro) it states the high byte of the number of refclk of the vertical sync period measurement. d7-4 reserved d3-0 vsprd[11:8] input v back porch count by input hs - low (address 52h) (ro) it states the low byte of the number of lines between the end of vsync and the active image. d7-0 vbpw[7:0] input v back porch count by input hs - high (address 53h) (ro) it states the high byte of the number of lines between the end of vsync and the active image d7-3 reserved d2-0 vbpw[10:8]
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 32 - 2000/06/14 input v active image count by input hs - low (address 54h) (ro) it states the low byte of the number of the active image lines. d7-0 vactw[7:0] input v active image count by input hs - high (address 55h) (ro) it states the high byte of the number of the active image lines d7-3 reserved d2-0 vactw[10:8] input v total image count by input hs - low (address 56h) (ro) it states the low byte of the number of the total image lines. d7-0 vtotw[7:0] input v total image count by input hs - high (address 57h) (ro) it states the high byte of the number of the total image lines. d7-3 reserved d2-0 vtotw[10:8] input hs period count by refclk - low (address 58h) (ro) it states the low byte of the number of refclks of the horizontal sync period measurement. d7-0 hsprd[7:0] input hs period count by refclk - high (address 59h) (ro) it states the high byte of the number of refclks of the horizontal sync period measurement. d7-5 reserved d4-0 hsprd[12:8] input h back porch count by input pixel clock -low (address 5ah) (ro) it states the low byte of the number of pixels between the end of hsync and the active image. d7-0 hbpw[7:0] input h back porch count by input pixel clock -high (address 5bh) (ro) it states the high byte of the number of pixels between the end of hsync and the active image. d7-3 reserved d2-0 hbpw[10:8] input h active image count by input pixel clock-low(address 5ch) (ro)
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 33 - 2000/06/14 it states the low byte of the number of the horizontal active image pixels. d7-0 hactw[7:0] input h active image count by input pixel clock-high(address 5dh)(ro) it states the high byte of the number of the horizontal active image pixels. d7-3 reserved d2-0 hactw[10:8] input h total image count by input pixel clock- low (address 5eh) (ro) it states the low byte of the number of the horizontal total image pixels. d7-0 htotw[7:0] input h total image count by input pixel clock- high (address 5fh) (ro) it states the high byte of the number of the horizontal total image pixels. d7-3 reserved d2-0 htotw[10:8] display vertical total - low (address 60h) (r/w) it defines the low byte of the number of lines per display frame. d7-0 dv_ total[7:0] display vertical total - high (address 61h) (r/w) it defines the high byte of the number of lines per display frame. d7-3 reserved d2-0 dv_ total[10:8] display vertical sync end - low (address 62h) (r/w) it defines the low byte of vertical sync end position in lines. d7-0 dv_sync_ end[7:0] display vertical sync end - high (address 63h) (r/w) it defines the high byte of vertical sync end position in lines. d7-3 reserved d2-0 dv_sync_ end[10:8] note: display vertical sync start is always equal 0.
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 34 - 2000/06/14 display vertical active start - low (address 64h) (r/w) it defines the low byte of vertical active region start position in lines. d7-0 dv_act_ start[7:0] display vertical active start - high (address 65h) (r/w) it defines the high byte of vertical active region start position in lines. d7-3 reserved d2-0 dv_act_ start[10:8] display vertical active end - low (address 66h) (r/w) it defines the low byte of vertical active region end position in lines. d7-0 dv_act_ end[7:0] display vertical active end - high (address 67h) (r/w) it defines the high byte of vertical active region end position in lines. d7-3 reserved d2-0 dv_ act_ end[10:8] display horizontal total - low (address 70h) (r/w) it defines the low byte of the number of display clock cycles per display line. d7-0 dh_ total[7:0] display horizontal total - high (address 71h) (r/w) it defines the high byte of the number of display clock cycles per display line. d7-3 reserved d2-0 dh_ total[10:8] display horizontal sync end - low (address 72h) (r/w) it defines the low byte of horizontal sync end position in display clock cycles. d7-0 dh_sync_ end[7:0] display horizontal sync end - high (address 73h) (r/w) it defines the high byte of horizontal sync end position in display clock cycles. d7-3 reserved d2-0 dh_sync_ end[10:8] note: display horizontal sync start is always equal 0.
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 35 - 2000/06/14 display horizontal active start - low (address 74h) (r/w) it defines the low byte of horizontal active region start position in display clock cycles. d7-0 dh_act_ start[7:0] display horizontal active start - high (address 75h) (r/w) it defines the high byte of horizontal active region start position in display clock cycles. d7-3 reserved d2-0 dh_act_ start[10:8] display horizontal active end - low (address 76h) (r/w) it defines the low byte of horizontal active region end position in display clock cycles. d7-0 dh_act_ end[7:0] display horizontal active end - high (address 77h) (r/w) it defines the high byte of horizontal active region end position in display clock cycles. d7-3 reserved d2-0 dh_act_ end[10:8] nfb timing control (address 7fh) it defines the nfb timing setting. d7-0 free running mode select 60h: normal 80h: free running output image control register 0 (address 88h) (r/w) d7-5 reserved d4 output port msb / lsb exchange 0: no exchange 1: exchange d3 reserved d2 output pixel 18 bit rgb mode select 0: 24 bit rgb 1: 18 bit rgb d1 output dual pixel data exchange 0: normal 1: exchange d0 output dual pixel select 0: dual pixel
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 36 - 2000/06/14 1: single pixel output image control register 1 (address 89h) (r/w) d7-6 res erved d5 rgb brightness control enable 0: disable 1: enable d4 rgb gain control enable 0: disable 1: enable d3-2 reserved d1 border window function 0: off 1: on d0 output blank screen 0: normal 1: output pixel masked as black colo r output image control register 2 (address 8ah) (r/w) d7 reserved d6 temporal dithering enable 0: static dithering 1: temporal dithering d5 reserved d4 dithering enable 0: disable 1: enable d3-2 reserved d1 gamma table r/w access en able 0: disable 1: enable d0 gamma correction function 0: off 1: on color gain control - red (address 90h) (r/w) it can be used to adjust the gain of red component of the display image. d7-0 rgain[7:0] 0(00h) ~ x1(80h) ~ x1.992185( ffh) color gain control - green (address 91h) (r/w)
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 37 - 2000/06/14 it can be used to adjust the gain of green component of the display image. d7-0 ggain[7:0] 0(00h) ~ x1(80h) ~ x1.992185( ffh) color gain control - blue (address 92h) (r/w) it can be used to adjust the gain of blue component of the display image. d7-0 bgain[7:0] 0(00h) ~ x1(80h) ~ x1.992185( ffh) color brightness control - red (address 93h) (r/w) it can be used to adjust the brightness of red component of the display image. d7-0 rbright[7:0] -128(80h) ~ 0(00h) ~127(7fh) color brightness control - green (address 94h) (r/w) it can be used to adjust the brightness of green component of the display image. d7-0 gbright[7:0] -128(80h) ~ 0(00h) ~127(7fh) color brightness control - blue (address 95h) (r/w) it can be used to adjust the brightness of blue component of the display image. d7-0 bbright[7:0] -128(80h) ~ 0(00h) ~127(7fh) border window color - red (address 96h) (r/w) when the display image is not expanded to full screen, it can be specified as the red component of the border color. d7-0 bcr[7:0] border window color - green (address 97h) (r/w) when the display image is not expanded to full screen, it can be specified as the green component of the border color. d7-0 bcg[7:0] border window color - blue (address 98h) (r/w) when the display image is not expanded to full screen, it can be specified as the blue component of the border color. d7-0 bcb[7:0] gamma table data port (address 9fh) (r/w) since the gamma table is downloadable, this data port is the entry address.
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 38 - 2000/06/14 d7-0 gamma_ port[7:0] osd control register 0 (address a0h) (r/w) d7 osd output clock select 0: from internal display dot clock 1: from internal display dot clock x 2 d6-4 reser ved d3 osd function 0: off 1: on d2 osd intensity enable (for motorola) 0: disable 1: enable d1-0 osd type select 00: osdrgb = { r 0000000, g 0000000, b 0000000} 01: osdrgb = { rr 000000, gg 000000, bb 000000} 10: osdrgb = { rrrr 0000, gggg 0000, bbbb 0000} 11: osdrgb = { rrrrrrrr , gggggggg , bbbbbbbb } r = osdr, g = osdg, b = osdb osd control register 1 (address a1h) (r/w) d7 osd output hs invert 0: normal 1: invert. d6 osd output dclk invert 0: normal 1: invert. d5-4 osd output hs delay 4 steps to change, each of them is 1ns delay/step. d3 osd input data sample clock invert 0: normal. 1: invert. d2-0 osd input data sample clock delay 8 steps to change, each of them is 1ns delay/step. output invert control (address a4h) (r/w) d7 reserved d6 rgb data invert enable 0: disable 1: enable d5 display dhclk invert 0: normal 1: invert
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 39 - 2000/06/14 d4 display dclk invert 0: normal 1: invert d3 reserved d2 display data enable (dden) invert 0: normal 1: invert d1 d isplay vsync invert 0: normal 1: invert d0 display hsync invert 0: normal 1: invert output tri_state control (address a5h) (r/w) d7 display data r2out, g2out, b2out output disable 0: normal 1: tri_stated d6 display data r1out, g1out, b 1out output disable 0: normal 1: tri_stated d5 display dhclk output disable 0: normal 1: tri_stated d4 display dclk output disable 0: normal 1: tri_stated d3 osd oclk / ovsync / ohsync output disable 0: normal 1: tri_stated d2 displ ay data enable (dden) output disable 0: normal 1: tri_stated d1 display vsync output disable 0: normal 1: tri_stated d0 display hsync output disable 0: normal 1: tri_stated output clocks delay adjustment (address a6h) (r/w) d7-4 displa y dhclk delay adjustment 16 steps to adjust, typical 1ns delay/step
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 40 - 2000/06/14 d3-0 display dclk delay adjustment 16 steps to adjust, typical 1ns delay/step output clocks duty cycle adjustment (address a7h) (r/w) d7 display dhclk duty cycle increase/decrea se 0: decrease 1: increase d6-4 display dhclk duty cycle adjustment 8 steps to adjust, typical 0.5ns delay/step d3 display dclk duty cycle increase/decrease 0: decrease 1: increase d2-0 display dclk duty cycle adjustment 8 steps to adjust , typical 0.5ns delay/step output miscellaneous control (address a9h) (r/w) d7 second field line buffer overflow status for interlace input (ro) 0: not overflow 1: overflow d6 second field line buffer underflow status for interlace input (ro) 0: not underflow 1: underflow d5 first field line buffer overflow status for interlace input or line buffer overflow status for non-interlace input (ro) 0: not overflow 1: overflow d4 first field line buffer underflow status for interlace in put or line buffer overflow status for non-interlace input (ro ) 0: not underflow 1: underflow d3 auto output horizontal total calculation start (w) 0: disable 1: enable auto output horizontal total calculation ready flag (r) 0: ready 1: not ready d2-0 reserved output vertical active line number - low (address aah) (r/w) it defines the low byte of output vertical active line number only used for getting the values of reg. ach and adh . d7-0 ovde[7:0] output vertical active line number - high (address abh) (r/w)
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 41 - 2000/06/14 it defines the high byte of output vertical active line number only used for getting the values of reg. ach and adh . d1-0 ovde[9:8] output horizontal total pixel number - low (address ach) (ro) it states the low byte of output horizontal total pixel number. d7-0 ohtot[7:0] output horizontal total pixel number - high (address adh) (ro) it states the high byte of output horizontal total pixel number. d2-0 ohtot[10:8] output horizontal total residue number - low (address aeh) (ro) it states the low byte of output horizontal total pixel residue number. d7-0 ohtot_ res[7:0] output horizontal total residue number - high (address afh) (ro) it states the high byte of output horizontal total pixel residue number. d1-0 ohtot_ res[9:8] zoom control register 0 (address b0h) (r/w) d7 reserved d6-4 vertical scale select 0xx: pass mode 10x: duplicate mode 110: bilinear mode 111: interpolation table mode d3 reserved d2-0 horizontal scale select 0xx: pass mode 10x: duplicate mode 110: bilinear mode 111: interpolation table mode zoom control register 1 (address b1h) (r/w) d7-1 reserved *d3 horizontal zoom factor mode 0: uniform scale mode 1: extension boundary scale mode *d2 vert ical zoom factor mode
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 42 - 2000/06/14 0: uniform scale mode 1: extension boundary scale mode d0 interpolation table r/w access enable 0: disable 1: enable zoom vertical scale ratio ? low (address b4h) (r/w) it defines the low byte of vertical scale ratio value for scale up. d7-0 zvsf[7:0] zoom vertical scale ratio - high (address b5h) (r/w) it defines the low byte of vertical scale ratio value for scale up. d7-0 zvsf[15:8] zvsf = ceil[( input_height ? 1) / ( output_height ? 1) *2 16 ] for uniform scale mode zvsf = ceil[( input_height / output_height) *2 16 ] for extension boundary scale mode zoom horizontal scale ratio - low (address b6h) (r/w) it defines the low byte of horizontal scale ratio value for scale up. d7-0 zhsf[7:0] zoom horizontal scale ratio - high (address b7h) (r/w) it defines the high byte of horizontal scale ratio value for scale up. d7-0 zhsf[15:8] zhsf = ceil[( input_width ? 1) / ( output_width ? 1) *2 16 ] for uniform scale mode zhsf = ceil[( input_width / output_width) *2 16 ] for extension boundary scale mode interpolation table data port (address bfh) (r/w) it defines the entry address of the interpolation table data port. d7-0 tfport[7:0] host control register 1 (address c1h) (r/w) d7 reserved d6 i2c bus address no increment 0: normal 1: no increment d5 double buffer load select 0: immediately 1: delay to display vsync d4 registers double buffer function enable 0: disable
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 43 - 2000/06/14 1: enable d3-2 reserved d1 display registers double buffer load (wo) d0 input registers double buffer load (wo) host access mode status (address cbh) (ro) d7-2 reserved d1-0 host access mode 0x: 3-wire serial mode 10: 2-wire serial mode (iic) 11: 8-bit parallel mode clock synthesizer control register (address e0h) (r/w) d7-0 display clock selection 40h: internal display clock (pll) note: reg. f1h/d3 must be 1. 25h: external display clock 1 a5h: external display clock 2 clock synthesizer value load (address e1h) (wo) d7-1 reserved d0 disp lay clock synthesizer value load ( wo) display clock synthesizer n value (address e2h) (r/w) d7-0 display clock synthesizer n value display clock synthesizer m value (address e3h) (r/w) d7-0 display clock synthesizer m value clock synthesizer r value (address e6h) (r/w) d7 reserved d6-4 refclk clock divider value 000: no divided 001: divided by 2 010: divided by 4 011: divided by 8 100: divided by 3 101: divided by 6 110: divided by 12 111: divided by 24 d3-2 rese rved d1-0 display clock synthesizer r value 00: no divided
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 44 - 2000/06/14 01: divided by 2 1x: divided by 4 sync interrupt flag control (address e8h) (r) it contains the status of sync interrupts. d7 display vsync pulse interrupt status 0: no display vsync pulse detected 1: any display vsync pulse detected d6 input vsync pulse interrupt status 0: no input vsync pulse detected 1: any input vsync pulse detected d5 vsync presence change status 0: no change 1: change d4 hsync presence chang e status 0: no change 1: change d3 vsync polarity change status 0: no change 1: change d2 hsync polarity change status 0: no change 1: change d1 vsync frequency change status 0: no change 1: change d0 hsync frequency change status 0: no change 1: change sync interrupt flag control (address e8h) (w) it is used to clear the corresponding sync interrupt signal when software finishes serving the interrupt service routine. d7 clear display vsync pulse interrupt enable 0: disab le 1: enable d6 clear input vsync pulse interrupt enable 0: disable 1: enable d5 clear vsync presence change interrupt enable 0: disable 1: enable d4 clear hsync presence change interrupt enable
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 45 - 2000/06/14 0: disable 1: enable d3 clear vsync pol arity change interrupt enable 0: disable 1: enable d2 clear hsync polarity change interrupt enable 0: disable 1: enable d1 clear vsync frequency change interrupt enable 0: disable 1: enable d0 clear hsync frequency change interrupt enable 0: disable 1: enable general interrupt flag control (address e9h) (r) it contains the status of general interrupts. d7-3 reserved d2 reserved d1 auto position finish status (valid for single mode only) 0: not finish 1: finish d0 auto c alibration finish status (valid for single mode only) 0: not finish 1: finish general interrupt flag control (address e9h) (w) it is used to clear the corresponding general interrupt signal when software finishes serving the interrupt service routine. d7-3 reserved d2 reserved d1 clear auto position finish interrupt enable 0: disable 1: enable d0 clear auto calibration finish interrupt enable 0: disable 1: enable sync interrupt flag enable (address eah) (r/w) it is used to enable sync interrupt function. d7 display vsync pulse interrupt enable
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 46 - 2000/06/14 0: disable 1: enable d6 input vsync pulse interrupt enable 0: disable 1: enable d5 vsync presence change interrupt enable 0: disable 1: enable d4 hsync presence change i nterrupt enable 0: disable 1: enable d3 vsync polarity change interrupt enable 0: disable 1: enable d2 hsync polarity change interrupt enable 0: disable 1: enable d1 vsync frequency change interrupt enable 0: disable 1: enable d0 hs ync frequency change interrupt enable 0: disable 1: enable general interrupt flag enable (address ebh) (r/w) it is used to enable general interrupt functions. d7-3 reserved d2 reserved d1 auto position finish interrupt enable 0: disable 1 : enable d0 auto calibration finish interrupt enable 0: disable 1: enable hs frequency change interrupt compare (address ech) (r/w) it is used to control interrupt generation by comparing the frequency change value when input hs frequency changes. d7-0 hscmpreg[7:0] power management control (address f1h) (r/w) d7 reserved
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 47 - 2000/06/14 d6 power down gamma & interpolation table 0: normal 1: power down d5 reserved d4 power down line buffers 0: normal 1: power down d3 power down oscillator pad 0: power down 1: normal d2 reserved d1 power down all the clocks except refclk 0: normal 1: power down d0 software reset enable 0: disable 1: enable gpio control register (address f4h) (r/w) it controls the data of the gpio pins. d7-4 reserved d3-0 gpio[3:0] gpio direction control (address f5h) (r/w) it controls the in/out direction of the gpio pins, where ? 0 ? means input, and ? 1 ? means output. d7-4 reserved d3-0 gpio[3:0] in/out select 0: input 1: output gpio misc control (address f6h) (r/w) it defines the gpio pins miscellaneous control. d7-1 reserved d0 gpio[1:0] output pins source 0: from reg. f4h gpio[1:0] 1: from advs/adhs
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 48 - 2000/06/14 5. electrical characteristics 5.1 dc characteristics table 5.1 recommended operating conditions symbol parameter min typ max unit vcc operation voltage 3.0 3.3 3.6 v tamb operating ambient temperature 0 70 o c tstg storage temperature -55 150 o c table 5.2 dc electrical characteristics for 3.3 v operation symbol parameter conditions min typ max unit vil input low voltage 0.8 v vih input high voltage 2.0 v vt- input schmitt trigger low voltage at pins sda and sck 1.0 vt+ input schmitt trigger high voltage at pins sda and sck 1.7 vol output low voltage 0.4 v voh output high voltage 2.4 v ri input pull-up/down resistance vil = 0v or vih = vcc 75 kohm ili input leakage current -10 10 ua ilo output leakage current -20 20 ua
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 49 - 2000/06/14 5.2 ac characteristics input interface timing figure 5.2.1 input interface timing table 5.2.1 input interface timing symbol parameter min max unit tids input image signal setup time for ipclk 2 ns tidh input image signal hold time for ipclk 3 ns tivhs input vsync/hsync setup time for ipclk 2 ns tivhh input vsync/hsync hold time for ipclk 3 ns tids tidh tivhh tivhs ipclk input vs/hs pixin[23:0]
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 50 - 2000/06/14 output interface timing figure 5.2.2 output interface timing table 5.2.2 output interface timing symbol parameter min max unit tdck display clock ddclk frequency 10 ns tdvs display vsync output delay to ddclk 2 ns tdhs display hsync output delay to ddclk 0.5 ns tdde display dden output delay to ddclk 1 ns tddp display data output delay to ddclk 1.5 ns note: ddclk phase can be adjusted relative to data and control outputs using the ddclk_inv (reg. a4h/d5-4) and ddclk_ delay[2:0] (reg. a6h/d7-0) programming controls. tdck tdde tdhs tddp tdvs ddclk display vs pixout1[23:0] / pixout2[23:0] display hs display dden
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 51 - 2000/06/14 osd interface timing figure 5.2.3 osd interface timing table 5.2.3 osd interface timing symbol parameter min max unit tosdd osd vs / hs output delay to oclk 2 ns tosds osd signal input setup time for oclk 5.5 ns tosdh osd signal input hold time for oclk 0 ns note: oclk phase can be adjusted using oclk_inv (reg. a1h/d3) programming control and ohsync phase can be adjusted using ohsync_delay[1:0] (reg. a1h/d5-4) programming control. tosdd tosds tosdh oclk input osdden / osdred / osdgrn / osdblu ovsync / ohsync
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 52 - 2000/06/14 i2c host interface timing figure 5.2.4 i2c host interface timing table 5.2.4 i2c host interface timing symbol parameter min max unit thigh clock high period 500 ns tlow clock low period 500 ns tsu:dat data in setup time 200 ns thd:dat data in hold time 100 ns tsu:sta start condition setup time 500 ns thd:sta start condition hold time 500 ns tsu:sto stop condition setup time 500 ns thd:sto stop condition hold time 500 ns tsu:dat thd:dat tsu:sta thd:sto tsu:sto thd:sta tlow thigh
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 53 - 2000/06/14 8-bit direct host interface timing figure 5.2.5 8-bit direct host interface timing table 5.2.5 8-bit direct host interface timing symbol parameter min max unit tavll address valid to ale low 3 ns tllax address hold after ale low 5 ns trwpw wr/rd pulse width 35 ns tllwl ale low to wr/rd low 5 ns tqvwh data valid to wr high 3 ns twhqx data hold after wr 10 ns twhlh wr/rd high to ale high ? register io r/w 0 ns trlaz rd low to address float -5 ns trldv rd low to valid data in 30 ns trhdz data float after rd high 0 15 ns tqvwh data in data out a0-a7 a0-a7 tavll tllax tllwl trwpw twhlh trhdz trldv h h h trlaz ad(7:0)/wr ad(7:0)/rd ale wr/rd
myson technology MTL004 ( rev. 0.95 ) revision 0.95 - 54 - 2000/06/14 aaa bbb seating plane 6. package dimension 120/128/132/144/160/184/208/256l ofp 28 x 28 x 3.32 mm 2.6mm footprint gage plane c 3 1 c ccc d a-b c ddd b e 4x a- b d h a- b d c 4x e e1 e2 d1 d2 d 0.05 a2 c ;l1 millimeter inch symbol min. nom. max . min. nom. max. a x x 4.10 x x 0.161 a1 0.25 x x 0.010 x x a2 3.20 3.32 3.60 0.126 0.131 0.142 d 30.60 bsc 1.205 bsc d1 28.00 bsc 1.102 bsc e 30.60 bsc 1.205 bsc e1 28.00 bsc 1.102 bsc r2 0.08 x 0.25 0.003 x 0.010 r1 0.08 x x 0.003 x x 0 3.5 7 0 3.5 7 1 0 x x 0 x x 2 8 ref 8 ref 3 8 ref 8 ref c 0.09 0.15 0.20 0.004 0.005 0.008 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.30 0.051 ref s 0.20 x x 0.008 x x notes: 1. dimensions d1 and e1 do not include mold protrusion. 2. simension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. dambar can not be located on the lower radius or the foot. the minimum space between protrusion and an adjacent lead shall not be less than 0.07 mm. 3. the top package booy size may be smaller than the bottom package booy size. min. nom. max. min. nom. max. 0.17 0.20 0.27 0.007 0.008 0.011 0.50 bsc. 0.020 bsc. 25.50 1.004 25.50 1.004 tolerances of form and position 0.20 0.008 0.20 0.008 x 0.08 x x 0.003 x x 0.08 x x 0.003 x a1 b a m s s s s 2 l 0.25mm r1 r2

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